IEEE-EPS Distinguish Lecture on Advanced Substrates

 

< IEEE-EPS Distinguish Lecture on Advanced Substrates >

**Free event**

IEEE-EPS (Electronics Packaging Society) Distinguished Lecture program is a prestigious initiative that invites expert speakers to deliver lectures on advanced topics related to electronics packaging.   

This year, we're honored to have Dr. John Lau, Senior Special Project Assistant of Unimicron to give a short lecture 

 

Time: 13:00-14:00, Oct 22nd (Tuesday)

Location: R504A, 5F, Taipei Nangang Exhibition Hall 1 

Fee: Free of charge(sponsored by IEEE-EPS)

Topic: Advanced Substrates for Chiplet and Heterogeneous Integrations

Lecture : Dr. John Lau, Senior Special Project Assistant of Unimicron

Language : English

Sign up link : https://docs.google.com/forms/d/e/1FAIpQLSchTC8NZDNPovvFWjUVrA_7nFVt3bSgDZGppozjNc0uSPCxxw/viewform

 

Abstract

Today, most of the package substrates driven by AI (artificial intelligence) are made by the 2.5D IC integration. In general, for 2.5D, the chips and high bandwidth memories (HBMs) are supported by a TSV-interposer and then solder bump and underfill on a build-up package substrate. However, because of the ever increasing size of the TSV-interposer, the manufacture yield loss of the TSV-interposer is becoming unbearable. In the past few years, 2.3D IC integration is getting lots of traction. The motivation is to replace the TSV-interposer with a fan out fine metal L/S redistribution-layer (RDL)-substrate (or organic-interposer). In general, for 2.3D, the package substrate structure (hybrid substrate) consists of a build-up package substrate, solder joints with underfill, and the organic-interposer. Today, 2.3D is already in production. During IEEE/ECTC 2023, TSMC published two papers on replacing the large-size TSV-interposer by LSIs (local silicon interconnects, i.e. Si bridges) and embedding the LSIs in fan-out RDL-substrate. TSMC called it CoWoS-L. Very recently, since Intel’s announcement (September 18, 2023) on the glass core substrate for their one-trillion transistors to be shipped before 2030, glass core substrate has been a very hot topic. In this lecture, the introduction, recent advances, and trends in 2.5D IC integration, 2.3D IC integration, CoWoS-L, and glass core substrate for high-performance computing (HPC) will be discussed.

 

Lecturer Bio

John H Lau, with more than 40 years of R&D and manufacturing experience in semiconductor packaging, has published more than 530 peer-reviewed papers (385 are the principal investigator), 52 issued and pending US patents (31 are the principal inventor), and 23 textbooks (all are the first author). John is an elected IEEE fellow, IMAPS Fellow, and ASME Fellow and has been actively participating in industry/academy/society meetings/conferences to contribute, learn, and share. 

 

Who Should Attend?

If you (students, engineers, and managers) are involved with any aspect of the electronics industry, you should attend this course. It is equally suited for R&D professionals and scientists. The lectures are based on the publications by many distinguish authors and the books (by the lecturer).